The invention relates generally to programmable dividing or counting circuitry. More specifically, the invention concerns high speed frequency dividers usable in such applications as phase-lock-loop frequency synthesizers or precision timers.
Two desirable properties of a programmable divider are that it operate at a high clock rate and that its division modulus be programmable in the smallest possible steps (integer steps are usually desired). In conventional approaches to programmable dividers, at least some of the circuitry containing the logic gates required for the divider to be programmable is clocked at the input frequency of the programmable divider, which limits the maximum clock frequency that can be used. This is due to the fact that the logic gates employed have inherent delays which in turn limit the maximum external clock frequency able to be used. Higher input frequencies are accommodated by using a divide-by-P fixed-modulus prescaler (where P is commonly 2 or 4) in a stage prior to the programmable divider. The fixed-modulus prescaler can run at a higher speed, since it need only contain latches with no logic gates between the latches. The prescaler normally supplies one clock pulse to the programmable divider for every N clock pulses presented to the prescaler input.
This conventional combination of a prescaler and a programmable divider reduces the possible division moduli to those that are integer multiples of the prescaler modulus N. The fundamental limitation of this conventional arrangement is that, each time the prescaler is driven through its internal cycle by N input clock pulses, only one internal transition of the prescaler wave form is used to clock the subsequently operating programmable divider. The timing information which exists in the remaining N-1 input pulses is not utilized in any way in the conventional approach, but is ignored, and therefore lost.
The concept of sensing all of the internal transitions of a divide-by-two circuit to generate timing signals for a high speed data multiplexer has been described previously in "A Bipolar 4:1 Time Division Multiplexer IC Operating Up To 5.5Gb/s", IEEE Solid-State Circuits Conference Digest of Technical Papers, pages 186-187, February, 1986, Reimann, R. and Rein, H.
However, it is believed that the concept has never before been extended to more general clocked logic circuitry, such as dividers and counters.
Additionally, there are no known high speed programmable non-integer dividers providing an arrangement for evenly spacing divider output pulses where division by non-integers is desired.
For example, in the prior art, division by N+1/2, where N is an integer, has been performed by alternately dividing by N and N+1. However, this known approach generates an undesirable subharmonic of the divider output, since the output pulses are unevenly spaced.
In the general case, non-integer division may be effected by alternating between N and N+1 in such a way as to provide an average count which is some desired fraction with a value between N and N+1. Heretofore, obtaining a divisor of N+a/b by dividing by N for "a" times and N+1 for (b-a) times produces an output with subharmonics down to l/b of the output frequency.
Therefore, there is seen to be a need for providing a programmable divider capable of generating evenly spaced output pulses for non-integer divisor values.